In recent years, the number and density of memory cells on a DRAM chip have dramatically increased. Areas of the DRAM chip on a substrate consist of an array of closely spaced memory cells with address and read/write circuits along the periphery of the DRAM chip. The individual DRAM cells (memory cells) are formed from a single access transistor, typically a field effect transistor (FET), and a storage capacitor with a node contact to one of the two source/drain areas of the FET. The capacitor is used for storing information in binary form (i.e., in values of 0 and 1) as an electrical charge, and the other of the two source/drain areas is connected to a bit line that is used to read and write information via peripheral circuits on the DRAM chip. Word lines that also form the FET gate electrodes over the active device (cell areas) are used to randomly access the individual memory cells.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.